Check Out Barreleye G2, Zaius at OpenPOWER, OpenCompute and IBM Think

Zaius motherboard in Barreleye G2 server

Rackspace is showcasing brand new Zaius PVT motherboard samples and Barreleye G2 servers at OpenPOWER Summit, Open Compute Summit and IBM Think next week, demonstrating their industry leading capabilities.

Zaius/Barreleye G2 OpenPOWER platform was originally announced at the OpenPOWER Summit in 2016 as collaborative effort between Google and Rackspace. Since then we have made steady progress on the development of this platform. We have navigated through engineering validation and test (EVT), design validation and test (DVT) and made various optimizations to the design resulting in refined solution. We continue to qualify various OpenCAPI/NVLink 2.0 adapters and play with frameworks (SNAP/PowerAI) that enable easy adoption of these adapters.

Here’s when and where we’re speaking at each conference:

IBM Think, Las Vegas 

OpenCAPI / NVLink Accelerators on Barreleye G2 OpenPOWER Server

March 19, 8:30 a.m., Mandalay Bay South, Level 2 | Reef C

OpenPOWER Summit, Las Vegas

Member Panel: Hardware

March 19, 10:25 a.m., MGM Grand Convention Center, Main Stage

Accelerators & Development Update: Zaius & Barreleye G2

MARCH 19, 1 p.m., MGM Grand Convention Center, Room 308

Open Compute Summit, San Jose

Accelerator Eco-System on Zaius / Barreleye G2 Server

March 21, 9:25 a.m., San Jose Convention Center, 211A

Tri-mode (SAS/SATA/NVMe) Storage Solution

March 21, 1 p.m., San Jose Convention Center, 210C

In these engineering workshops, Rackspace will detail our journey working with high speed IO, accelerators and our results; where possible we will request collaboration from the community to adjust Open Compute or OpenPOWER specifications to make accelerator adoption easier.

Our Zaius motherboard has just entered the production validation and test stage, which reflects our confidence in this design and our continued effort to bring OpenCAPI/NVLink 2.0/PCIe Gen4 accelerators to datacenters via this server housing IBM Power9 processors.

Also at the events, Rackspace will display our unique, disaggregated implementation of CPU-GPU NVLink 2.0 (50GBps) via SlimSAS to SXM2 interposer board. This will help Barreleye G2 servers to support NVLink Volta GPUs and other FPGA HBM2 solutions, ideal for artificial intelligence, deep learning and GPUDB applications.

SlimSAS – to – SXM2 Interposer for support Volta GPU and FPGA HBM2 Card

Further, when combined with PCIe Gen4, we believe this board will provide reference to the JBoG designs (Just a bunch of GPUs) in server industry for solving the two bottlenecks: the slow CPU-GPU link and a slow server-to-server network speed. Both of these bottlenecks are commonplace today in PCIe Gen3 servers, including HGX-1 Volta and Big Basin Volta.

Conference attendees will also get to see some first-in-industry technology demos from us, including PCIe Gen4 NVMe Storage, 1 Tbps server-to-server network bandwidth, Tri-mode storage (SAS-SATA-NVMe) hot-swap, 48V Power-shelf with Integrated ATS and OpenCAPI bandwidth test (25.78215 Gbps).

Tri-mode (SATA-SATA-NVMe) storage implementation on Rackspace’s Barreleye G2 server will be detailed. In the absence of industry moving on U.3 connectors, drives and  tri-mode expanders, we have creatively implemented a U.2 tri-mode solution by dual-wiring the existing storage connectors.

Barreleye G2 48V Rack & Delta Power Shelf with ATS

We expect to do limited access customer betas later this year, based on Barreleye G2 Accelerator servers. Customers interested in participating, please reach out to us.

Adi Gangidi is a Senior Systems Design Engineer at Rackspace, focused on OpenPOWER and Open Compute initiatives. He helps build and scale the next generation, cost-effective openPOWER Barreleye / Zaius Servers, featuring IBM POWER 8/9 processors. He is excited about the efficiency these servers bring to the datacenter in a post Moore's law era. He does whatever it takes for these initiatives to get into production: from low level hardware debug to building high-level cost models for the program. In past, he has worked with variety of FPGAs, embedded hardware and image processing algorithms in various roles. He received his MSEE from University of Massachusetts and his BSEE from BITS Pilani. When not working, he loves spending time with his wife, critiquing movies and visiting national parks.